Embodiments relate to a method of manufacturing a semiconductor device and devices thereof. Some embodiments relate to a MIM capacitor of a semiconductor device and methods of forming the same.
Capacitors may be used in semiconductor devices and may be classified as PIP (Poly Insulator Poly) capacitors and/or MIM capacitors, for example depending on a structure. Such capacitors may have unique characteristics and/or may be selectively used in accordance with characteristics of semiconductor devices. A MIM capacitor may be employed in a semiconductor device which may use a relatively high frequency. A PIP capacitor may have an upper electrode and/or a lower electrode, which may include conductive polysilicon. Oxidization may occur at an interface between an upper electrode and/or lower electrode and a thin insulator film, which may minimize capacitance. A MIM capacitor may have minimized resistivity, substantially no parasitic capacitance due to internal depletion and/or relatively high capacitance. In a semiconductor device using a relatively high frequency, device characteristics may vary due to RC delay, and a MIM capacitor including a metal having a maximized electrical characteristic may be used.
A MIM capacitor may be implemented at substantially the same time with a different semiconductor device to be electrically connected to the semiconductor device through a metal interconnect serving as a connection wire. Example FIG. 1A to FIG. 1D are views illustrating a method of forming a MIM structure and/or a metal layer. Referring to FIG. 1A, a lower metal wire may be formed on and/or over an oxide film, which may be formed on and/or over a semiconductor substrate. First TiN layer 102 may be formed, aluminum (Al) layer 104 may be formed and/or second TiN layer 106 may be formed, for example on and/or over formed aluminum layer 104. Referring to FIG. 1B, SiN layer 108 may be formed on and/or over second TiN layer 108, and/or third TiN layer 110 may be formed. First photoresist pattern 112 may be formed on and/or over third TiN 110, such that a MIM structure may be formed.
Referring to FIG. 1C, etching may be performed using first photoresist pattern 112 as a mask. A MIM structure may be formed on and/or over oxide film 100 of a semiconductor substrate. Referring to FIG. 1D, selective etching may be performed using a second photoresist pattern as a mask to form a metal layer. Metal layer 114 may be formed, and/or an inter-metal dielectric (IMD) 112 may be deposited on and/or over a surface, which may be the entire surface, of a semiconductor substrate. A MIM structure (106, 108, 110) and/or metal layer 114 may be formed.
In a method of manufacturing a MIM capacitor, photoresist patterns to form a MIM structure and/or subsequent metal layers may be formed individually. In addition, the process may use photoresist patterns as masks. In forming a MIM structure and/or a metal layer, a MIM capacitor and/or a subsequent metal layer may be formed separately. Two masks may need to be provided to form a MIM pattern and/or a metal pattern. Therefore, process time may be maximized, for example to form a metal layer.
Accordingly, there is a need for a method of manufacturing a MIM structure and devices thereof, which may minimize process time. There is a need of method of manufacturing a MIM capacitor, and devices thereof, that may form a MIM structure, for example within a hole with a single process, to form a metal/insulator/metal (MIM) structure and/or a subsequent metal layer structure.